USING STANDARD HARDWARE ACCELERATORS TO DECREASE COMPUTATION TIMES IN SCIENTIFIC APPLICATIONS

Authors

  • Dawid Kuna Academic Computer Centre CYFRONET AGH
  • Ernest Jamro University of Science and Technology, Academic Computer Centre CYFRONET AGH
  • Paweł Russek University of Science and Technology, Academic Computer Centre CYFRONET
  • Kazimierz Wiatr University of Science and Technology, Academic Computer Centre CYFRONET

DOI:

https://doi.org/10.7494/csci.2009.10.3.65

Keywords:

general-purpose processors, standard accelerators, computation accelerators, dedicated architectures, custom computing, GPGPU, Cell, ClearSpeed

Abstract

Nowadays, general-purpose processors are being used in scientific computing. However, whenhigh computational throughput is needed, it’s worth to think it over if dedicated hardwaresolutions would be more efficient, either in terms of performance (or performance to price ratio),or in terms of power efficiency, or both. This paper describes them briefly and comparesto contemporary general-purpose processors’ architecture.

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Author Biographies

Ernest Jamro, University of Science and Technology, Academic Computer Centre CYFRONET AGH

Department of Electronics AGH

Paweł Russek, University of Science and Technology, Academic Computer Centre CYFRONET

Department of Electronics AGH

Kazimierz Wiatr, University of Science and Technology, Academic Computer Centre CYFRONET

Department of Electronics AGH

References

Armstrong D. N., Hyesoon Kim, Mutlu O., Patt Y. N.: Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and Recovery, in: Proceedings of the 37th annual IEEE/ACM International

Symposium on Microarchitecture, MICRO 37, Portland, Oregon, 2004

Torng H. C., Day M.: Interrupt Handling for Out-of-Order Execution Processors. IEEE Transactions on Computers, vol. 42, 1993, 122–127

NVIDIA GeForce GTX 200 GPU Architectural Overview. Available on: http://www.nvidia.com/attach/1539847?type=support&primitive=0, 2008

NVIDIA CUDA Compute Unified Device Architecture Programming Guide. Available on: http://developer.download.nvidia.com/compute/cuda/2 0/docs/ NVIDIA CUDA Programming Guide 2.0.pdf, Version 2.0, 2008

Barker K., Davis K., Hoisie A., Kerbyson D., Lang M., Pakin S., Sancho J. S.: Experiences in Scaling Scientific Applications on Current-generation Quad-core Processors, in: Proceedings of the Workshop on Large-Scale Parallel Processing (LSPP’08)/International Parallel and Distributed Processing Symposium (IPDPS), Miami, Florida, 2008

Moreno R., Pi˜nuel L., del Pino S., Tirado F.: A Power Perspective of Value Speculation for Superscalar Microprocessors, in: Proceedings of the 2000 IEEE International Conference on Computer Design: “VLSI in Computers & Processors” (ICCD’00), Austin, TX, USA, 2000

Talla D., John L. K., Burger D.: Bottlenecks in multimedia processing with SIMD style extensions and architectural enhancements. IEEE Transactions on Computers, vol. 52, 2003, 1015–1031

Moshovos A., Sohi G. S.: Microarchitectural Innovations: Boosting Microprocessor Performance Beyond Semiconductor Technology Scaling. Proceedings of the IEEE, vol. 89, 2001, 1560–1575

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Published

2013-03-20

How to Cite

Kuna, D., Jamro, E., Russek, P., & Wiatr, K. (2013). USING STANDARD HARDWARE ACCELERATORS TO DECREASE COMPUTATION TIMES IN SCIENTIFIC APPLICATIONS. Computer Science, 10(3), 65. https://doi.org/10.7494/csci.2009.10.3.65

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Articles