COMPUTATION ACCELERATION ON SGI RASC: FPGA BASED RECONFIGURABLE COMPUTING HARDWARE

Ernest Jamro, Marcin Janiszewski, Krzysztof Machaczek, Paweł Russek, Kazimierz Wiatr, Maciej Wielgosz

Abstract


In this paper a novel method of computation using FPGA technology is presented. In severalcases this method provides a calculations speedup with respect to the General PurposeProcessors (GPP). The main concept of this approach is based on such a design of computinghardware architecture to fit algorithm dataflow and best utilize well known computingtechniques as pipelining and parallelism. Configurable hardware is used as a implementationplatform for custom designed hardware. Paper will present implementation results ofalgorithms those are used in such areas as cryptography, data analysis and scientific computation.The other promising areas of new technology utilization will also be mentioned,bioinformatics for instance. Mentioned algorithms were designed, tested and implemented onSGI RASC platform. RASC module is a part of Cyfronet’s SGI Altix 4700 SMP system. Wewill also present RASC modern architecture. In principle it consists of FPGA chips and veryfast, 128-bit wide local memory. Design tools avaliable for designers will also be presented.

Keywords


custom computing; single-purpose processors; FPGA; high performance computing; SGI RASC

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References


Bloom B. H.: Space/time trade-offs in hash coding with allowable errors. Commun. ACM, 13(7), pp. 422–426, 1970

Dongarra J. J., Du Croz J., Hammarling S., Duff I. S.: A set of level 3 basic linear algebra subprograms. ACM Trans. Math. Softw., 16(1), pp. 1–17, 1990

Doss C. C., Riley R. L. Jr.: Fpga-based implementation of a robust ieee-754 exponential unit. In FCCM ’04: Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 229–238, Washington,

DC, USA, 2004. IEEE Computer Society

Faria D. B., Cheriton D. R.: Dos and authentication in wireless public access networks. In WiSE ’02: Proceedings of the 1st ACM workshop on wireless security, pp. 47–56, New York, NY, USA, 2002. ACM

Silicon Graphics. SgiR rasct rc100 blade, dramatic application speed-up with next generation reconfigurable compute technology. http://www.sgi.com

Harris B., Jacob A. C., Lancaster J. M., Buhler J., Chamberlain R. D.: A banded smith-waterman fpga accelerator for mercury blastp. International Conference on Field Programmable Logic and Applications, 2007, FPL 2007, pp. 765–769, 27–29 Aug. 2007

He C., Lu M., Sun C.: Accelerating seismic migration using fpga-based coprocessor platform. In FCCM ’04: Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 207–216, Washington, DC, USA, 2004. IEEE Computer Society

Jamro E., Wiatr K., Wielgosz M.: Fpga implementation of 64-bit exponential function for hpc. International Conference on Field Programmable Logic and Applications, 2007, FPL 2007, pp. 718–721, 27–29 Aug. 2007

Wielgosz M., Piteron M., Jamro E., Russek P., Wiatr K.: Two electron integrals calculation accelerated with double precision exp() hardware module. Reconfigurable Systems Summer Institute, RSSI proceedings, July 2007

Montgomery P. L.: Modular multiplication without trivial division. Mathematics of Computation, pp. 519–521, 1985

Prasanna V. K.: Energy-efficient computations on fpgas. J. Supercomput., 32(2), pp. 139–162, 2005

Federal Information Processing. Fips pub 197, advanced encryption standard (aes), November 2001

Rivest R. L., Shamir A., Adelman L. M.: A method for obtaining digital signatures and public-key cryptosystems. Technical Report MIT/LCS/TM-82, 1977

Wiatr K., Russek P.: Dedicated architecture for double precision matrix multiplication in supercomputing environment. IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Cracow, April 2007

Xilinx. Virtex-4 User Guide. http://www.xilinx.com, 2007

Zhang P., Tan G., Gao G. R.: Implementation of the smith-waterman algorithm on a reconfigurable supercomputing platform. In HPRCTA ’07: Proceedings of the 1st international workshop on High-performance reconfigurable computing technology and applications, pp. 39–48, New York, NY, USA, 2007. ACM




DOI: https://doi.org/10.7494/csci.2008.9.3.21

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