Wojciech Wójcik, Jacek Długopolski


The paper presents the results of investigations concerning the possibilities of using programmable logic devices (FPGA) for building virtual multi-core processors dedicated to the chosen application. The paper shows the designed architecture of multi-core processor specialized for performing a particular task and discuss its computation efficiency depending on the number of cores being used. The evaluation of the results are also discussed.


Microprocessor, FPGA, Parallel Computing, Block Cipher

Full Text:



Yiannacouras P., Rose J., and Steffan J. G.: The Microarchitecture of FPGA Based Soft Processors, International Conference on Compilers, Architecture andSynthesis for Embedded Systems (CASES), September 2005, San Francisco, CA.

Coyne J., Cyganski D., Duckworth R. J.: FPGA-Based Co-processor for Singular Value Array Reconciliation Tomography. In Kenneth L. Pocek, Duncan A. Buell, editors, 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2008, 14-15 April 2008, Stanford, Palo Alto, California, USA. pages 163-172, IEEE Computer Society, 2008

Stanley Y. C. Li, Gap C. K. Cheuk, Kin-Hong Lee, Philip HengWai Leong,: FPGAbased SIMD Processor. In 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 8-11 April 2003, Napa, CA, Proceedings. pages 267-268, IEEE Computer Society, 2003

Zwolinski M.: Projektowanie układów cyfrowych z wykorzystaniem jezyka VHDL. wyd. 1., Warszawa, WKŁ 2007, ISBN 978-83-206-1635-4

Zainalabedin N.: Digital design and implementation with field programmable devices, XVI, Norwell, Kluwer Academic Publishers 2005, ISBN 1-4020-8011-5

Praca zbiorowa / red. Karbowski A., Niewiadomska-Szynkiewicz E.: Obliczenia 24 stycznia 2013 str. 15/16 równoległe i rozproszone, Warszawa, Oficyna Wydaw. Politechniki Warszawskiej 2001, ISBN 83-7207-234-5

DOI: https://doi.org/10.7494/csci.2013.14.3.459


  • There are currently no refbacks.