FPGA-based DVCPRO HD Decoder Implementation Using Impulse C

Slawomir Cichon; Marek Gorgon

doi:10.7494/csci.2013.14.4.531

Authors

Slawomir Cichon
Marek Gorgon

DOI:

https://doi.org/10.7494/csci.2013.14.4.531

Keywords:

high definition, video decoding, high level languages, pipelined architecture, intra-frame

Abstract

To be completed.

Downloads

Download data is not yet available.

References

Xu Shou-Gen, Wang Ming-Jiang, Zuo Shi-Kai: “A new hardware architecture for H.264 intraprediction frame processing”, IEEE 5th International Conference on Internet Multimedia Systems Architecture and Application (IMSAA), 2011.

M. Staworko, D. Modrzyk: “A high-performance VLSI architecture of 2D DWT processor for JPEG2000 encoder”, Proceedings of the 18th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), 2011.

Yi-Mao Hsiao, Feng-Pin Chang, Yuan-Sun Chu: “High speed multimedia network ASIC design for H.264/AVC”, The 5th IEEE Conference on Industrial Electronics and Applications (ICIEA), 2010.

R. Rodriguez, J. L. Martinez, G. Fernandez-Escribano, J. M. Claver, J. L. Sanchez: “Accelerating H.264 inter prediction in a GPU by using CUDA”, International Conference on Consumer Electronics (ICCE), 2010 Digest of Technical Papers.

Ngai-Man Cheung, Xiaopeng Fan; Au, O.C., Man-Cheung Kung: “Video Coding on Multicore Graphics Processors”, IEEE Signal Processing Magazine, pp. 79-89, vol.27, issue 2, March 2010.

B. Pieters, J. De Cock, C. Hollemeersch, J. Wielandt, P. Lambert, R. Van de Walle: “Ultra High Definition video decoding with Motion JPEG XR using the GPU”, 18th IEEE International Conference on Image Processing (ICIP), 2011.

Chanho Lee, Seohoon Yang: “Design of an H.264 decoder with variable pipeline and smart bus arbiter”, International SoC Design Conference (ISOCC), 2010.

Sangchul Kim, Hyunjin Kim, Taeil Chung, Jin-Gyeong Kim: “Design of H.264 video encoder with C to RTL design tool”, International SoC Design Conference (ISOCC), 2012.

A. B. Kinsman, N. Nicolici: “A VLSI Architecture and the FPGA Prototype for MPEG-2 Audio/Video Decoding”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 499-503, vol. 19, issue 3, 2011

Huang, H.-J., Fang, C.-H., Fan, C.-P.: “Very-large-scale integration design of a low-power and cost-effective context-based adaptive variable length coding decoder for H.264/AVC portable applications”, IET Image Processing, pp. 104-114, vol. 6, issue 2, 2012.

Junming Shan, Chunchun Chen, Yang, E.: “High performance 2-D IDCT for Image/Video Decoding based on FPGA”, International Conference on Audio, Language and Image Processing (ICALIP), 2012.

E. Kalali, Y. Adibelli, I. Hamzaoglu: “A high performance and low energy intra prediction hardware for HEVC video decoding”, Conference on Design and Architectures for Signal and Image Processing (DASIP), 2012.

P. Greisen et al.: "An FPGA-based processing pipeline for high definition stereo video", EURASIP Journal on Image and Video Processing 2011, 2011:18.

CoDeveloper User Guide, Impulse Accelerated, 2013: http://www.impulseaccelerated.com/ReleaseFiles/Help/iAppMan.pdf

SMPTE: Data Structure for DV-Based Audio, Data and Compressed Video at 100 Mb/s 1080/60i, 1080/50i, 720/60p, 720/50p, SMPTE Standard, SMPTE 370M-2006.

S. Cichoń, M. Gorgoń, M. Pac: “Handel-C design enhancement for FPGA-based DV decoder”, Reconfigurable computing, ARC, 2006, pp. 128-133.

M. Gorgoń: “Architektury rekonfigurowalne do przetwarzania i analizy obrazu oraz dekodowania cyfrowego sygnału wideo”, UWND AGH, Kraków 2007.

CENELEC: Recording – Helical-scan digital video cassette recording system using 6,35 mm magnetic tape for consumer use (525-60, 625-50, 1125-60 and 1250-50 systems). Part 2: SD format for 525-60 and 625-50 systems (IEC 61834-2:1998)

SMPTE: Data Structure for DV-based Audio, Data and Compressed Video 25 and 50 Mb/s, SMPTE Standard, SMPTE 314M-1999.

Ch. Loeffler, A. Ligtenberg, G.S. Moschytz: “Practical Fast 1-DCT Algorithms with 11 Multiplications”, Proc. of the International Conference on Acoustics, Speech, and Signal Processing, 1989, pp. 988–991.

J. van Eijndhoven, F. Sijstermans: “Data Processing Device and method of Computing the Cosine Transform of a Matrix”, PCT Patent No, WO 9948025, 1999.

W. H. Chen, C. H. Smith, and S. C. Fralick: “A fast computational algorithm for the discrete cosine transform”, IEEE Transactions on Communications, vol. 25, no.9, pp. 1004-1009, Sept. 1977.

Libdv webpage: http://sourceforge.net/projects/libdv/.

MainConcept, TotalCode Studio webpage: http://www.mainconcept.com/products/apps-plug-ins/transcoding/reference.html.

DRC Computing, Accelium Coprocessors Product Datasheet webpage: http://www.drccomputer.com/pdfs/DRC_Accelium_Coprocessors.pdf.