Study of OpenCL processing models for FPGA device


  • Piotr Szkotak Nordic Semiconductor Poland
  • Pawel Russek AGH University, Krakow, Poland Department of Electronic and ACC Cyfronet AGH
  • Kazmierz Wiatr AGH University, Krakow, Poland Department of Electronic and ACC Cyfronet AG



OpenCL, recongurable computing, accelerated computing, high-level hardware synthesis


In our study, we present the results of the implementation of SHA-512 algorithm in FPGA. The distinguished element of our work is that we conducted the work using OpenCL for FPGA which is a relatively new development method for reconfigurable logic. We examine the loop unrolling; as the OpenCL performance optimisation method, and compare the efficiency of the different kernel implementation types: NDRange, Single-Work Item, and SIMD kernels. In conclusions, we compare metrics of the created FPGA accelerator to the corresponding GPGPU solutions. Also, our paper is accompanied by the source code repository to allow the reader to follow and extend our survey.


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How to Cite

Szkotak, P., Russek, P., & Wiatr, K. (2019). Study of OpenCL processing models for FPGA device. Computer Science, 20(1).




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