ADAMSKI, Dominik; JABŁOŃSKI, Grzegorz. Hardware aware tiling optimization for multi-core systems. Computer Science, [S. l.], v. 18, n. 2, p. 145, 2017. DOI: 10.7494/csci.2017.18.2.145. Disponível em: https://journals.agh.edu.pl/csci/article/view/1867. Acesso em: 14 mar. 2025.